Load¶
lma - Load symbol address¶
-
lma rt sym
- Load symbol address into general register.Summary: rt = &symType code.No implicit register usage.
Parameters: - rt (GeneralRegister) – Receives address. Required. Output only.
- sym (symbol) – Symbol to load address of. Required. Input only.
lmbz - Load symbol byte and zero¶
-
lmbz rt sym d?
- Load zero extended byte from symbol into general register.Summary: rt = ext0(byte sym.d)Type code.No implicit register usage.
Parameters: - rt (GeneralRegister) – Receives value. Required. Output only.
- sym (symbol) – Symbol to load from. Variable address addend. Required. Input only.
- d (SignedInteger16b) – Displacement. Byte offset from symbol. Constant address addend. Optional. Default 0.
lvxu - Load vector indexed unaligned¶
-
lvxu vt ra rb ri? vi? vp?
- Load vector register from potentially unaligned memory.Indexed address specification.Works for aligned and unaligned memory.Type code.Abstracts on
endian
.Leaves undefined: ri vi vpRegister usageri Address calculationvi Intermediate loadvp Permute controlParameters: - vt (VectorRegister) – Receives value. Required. Output only.
- ra (0|GeneralRegister) – Address addend. Required. Input only.
- rb (GeneralRegister) – Address addend. Required. Input only. May not be r0.
- ri (GeneralRegister) – Address calculation. May not be ra. Optional. Default r11. Internal.
- vi (VectorRegister) – Intermediate load. May not be vt. Optional. Default v17. Internal.
- vp (VectorRegister) – Permute control. May not be vt vi. Optional. Default vp. Internal.
Raises: - Error – If ri is ra. Usage conflicts.
- Error – If vi is vt. Usage conflicts.
- Error – If vp is vt. Usage conflicts.
- Error – If vp is vi. Usage conflicts.
lvxu_be - Load vector indexed unaligned, big endian¶
-
lvxu_be vt ra rb ri? vi? vp?
- Big endian variant of
lvxu
.
lvxu_le - Load vector indexed unaligned, little endian¶
-
lvxu_le vt ra rb ri? vi? vp?
- Little endian variant of
lvxu
.